Internal Registers And Asi Operations; Accessing Mmu Registers - Fujitsu SPARC JPS1 Implementation Supplement Manual

F.10

Internal Registers and ASI operations

F.10.1

Accessing MMU Registers

IMPL. DEP. #233
Primary/Secondary/Nucleus TSB Extension Register is implementation dependent
in JPS1.
On SPARC64 V, the TSB_Hash field is not implemented in the I/D
Primary/Secondary/Nucleus TSB Extension Register. See TSB Pointer Formation
on page 88 for details.
IMPL. DEP. #239
virtual addresses 40000
See impl. dep. #235 in I/D TLB Data In, Data Access, and Tag Read Registers on page
93.
Additional information: The ASI_DCUCR register also affects the MMUs.
ASI_DCUCR is described in Section 5.2.12 of Commonality. The SPARC64 V
implementation dependency in ASI_DCUCR is described in Data Cache Unit Control
Register (DCUCR) on page 22.
SPARC64 V also has an additional MMU internal register ASI_MCNTL (Memory
Control Register) that is shared between the IMMU and the DMMU. The register is
illustrated in
ASI_MCNTL (Memory Control Register)
ASI:
VA:
Access Modes: Supervisor read/write
reserved
63
FIGURE F-1
92 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
: Whether the TSB_Hash field is implemented in I/D
: The register(s) accessed by IMMU ASI 55
to 60FF8
16
and described in
FIGURE F-1
45
16
08
16
NC_
Cache
17 16
Format of
ASI_MCNTL
are implementation dependent.
16
.
TABLE F-3
fw_ fw_
RMD 000
fITLB fDTLB
15 14 13 12 11
and DMMU ASI 5D
16
JPS1_TSBP 00000000
9 7
8
at
16
0