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P.4
Urgent Error
This section presents details about urgent errors: status monitoring, actions, and
end-methods.
P.4.1
URGENT ERROR STATUS (ASI_UGESR)
[1]
[2]
[3]
[4]
[5]
[6]
The ASI_UGESR register contains the following information when an
async_data_error
Detected
The type of second error to cause multiple
TABLE P-11
the name field have the following meaning:
IUG_
IAG_
IAUG_
ASI_UGESR
TABLE P-11
Bit
Name
Each bit in ASI_UGESR<22:8> indicates the occurrence of its corresponding error in a single-
0:
The error is not detected.
1:
The error is detected.
Each bit in ASI_UGESR<22:16> indicates an error in a CPU register. The error detection conditions for these
errors are defined in Handling of Internal Register Errors on page 181.
Release 1.0, 1 July 2002
Ideal specification (not implemented)
The EE_OTHER bit is specified in ASI_STCHG_ERROR_INFO bit 14. When
hardware detects error_state transition errors other than those described
above, it sets ASI_STCHG_ERROR_INFO.EE_OTHER = 1.
Register name:
ASI:
VA:
Error checking:
Format & function:
Initial value at reset:
(
) exception is generated.
ADE
s and
I_UGE
A_UGE
describes the fields of the ASI_UGESR register. In the table, the prefixes in
Instruction Urgent error
Autonomous Urgent error
The error detected as both
Bit Description (1 of 4)
RW
Description
ASI_URGENT_ERROR_STATUS
4C
16
08
16
None
See
.
TABLE P-11
Hard POR: All fields are set to 0.
Other resets: The values of all ASI_UGESR fields are
unchanged.
s, and related information
async_data_error
and
I_UGE
A_UGE
traps
trap as follows:
ADE
F. Chapter P
Error Handling
165
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