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Model 4025 Film Footage Encoder Manual
6.8.2. Character Generator Logic (6231-32)
The character display is formatted to display 28 (32 for PAL) rows of 32
characters each in the tiny size, 14 (16 for PAL) rows the small size, and 7
(8 for PAL) rows in the large size.
Each of the character positions
corresponds to one location in static RAM U9. The MCU writes characters
into specified locations in the RAM corresponding to the position of the
characters on the screen.
RAM locations are scanned during each
television field. Valid characters address corresponding sections of the
character PROM U8 and are loaded into the LCA one byte (8 bits) at a
time. Each byte corresponds to either the left or right half of a character
pixel line.
The internal logic in the LCA control how many lines per
character, and how many character lines there are on the raster, according
to registers set by the firmware.
The character data is clocked out of the LCA on the KEYFILL output ( U7
pin 7). A special character with all bits set to 1 is written into all positions of
the RAM where no characters are to be displayed.
These characters
disable the keyer by the KEY signal, generated in the LCA (U7 pin 6).
When other characters are present the KEY signal becomes active,
allowing the characters to be keyed into the video signal. The character
data is clocked out of the LCA with the dot clock, so that the pixel width is
not dependent on propagation delays in the LCA. The pixels are presented
to the video keyer when the VITC/CHAR signal is HIGH. A control register
in the LCA selects whether the characters will be white or black, and
whether they will be keyed into a contrasting background. Character style
selection is accomplished by the on screen programming menu.
6.8.3. Character Position and Size (6231-33)
The pixel oscillator consists of monostable U11b and associated
components. The oscillator frequency, which determines horizontal size, of
the characters is adjusted by
the digital trimpot (NVPOT) U13 and
associated components. The MCU writes different values to the NVPOT
which control the adjustment input to voltage regulator U12, which in turn
sets the voltage present for the RC timing network of the monostable. The
starting position of the characters at the left of the screen is controlled by
U11-A. Resistor R27 may be replaced to alter the left position of the
characters. Starting with board revision 6231A1, trim pot VR3 can be also
used to adjust the character left edge.
6.8.4. Video Circuits (6231-31)
Composite video, which comes up the submodule header from the main
board (J1 pins 1 and 2) is AC coupled and buffered by Q1 before going
into the sync separator LM1881 U4. The sync separator provides H Sync,
V Sync, a Frame pulse (active low for field 1) and a back porch clamp
pulse to drive the DC restorer circuitry U1, Q2, and Q3 and associated
components. The back porch clamp pulse allows U1 to compare the actual
DC level of the video to ground potential.
If they are not equal, U1
generates an error signal which adjusts the bias point of Q2 thus ensuring
proper operation of the video keyer with varying video and sync levels.
TECHNICAL DESCRIPTION
Page 6-24
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