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TECHNICAL DESCRIPTION
A GENLOCK Field 1 pulse, generated by the 615 module, is received by
U18 (jumper J6 must be in the G position) where it is inverted and sent to
the MCU. This pulse is used to provide a proper gen-lock reference to the
reader, irrespective of the input video to the 611 reader.
6.6.2. High Speed LTC Reader (6110-30)
Incoming code is decoupled and amplified by U8, U7, and U4, and
associated components, to provide a regenerated reader data signal at U4
pin 4. A series of timing pulses, generated by U3 and U5, are used to
properly decode 0 and 1 bits from the incoming code.
amplitude ramp is generated by U12 and associated components. Three
quarters of the peak ramp level is used as a reference on comparator U1 to
decode the data from the clock transitions. If the next code bit is a 0, then
the ramp will exceed the reference before a transition occurs. If the next bit
is a 1, an extra transition will occur before the ramp exceeds the reference,
clocking flip flop U5a on. The LTC data is available at U5a pin 1, and is
shifted through sync detector U19 and U21 into one half of shift register
U16.
Twelve consecutive 1 bits, detected by U20, clock flip flop U15a on,
freezing the sync word data at the outputs of U19 and U21, and generating
an LTC RDY signal to the MCU when it has received one frame of data.
Direction information (LTC DIR), derived from the last bit of the sync word
is also fed to the MCU. A valid reader sync word toggles flip flop U15b,
enabling the other half of shift register U16 to collect data from the next
frame while the MCU is unloading data from the frame just completed
through switch U17.
6.6.3. Video Processing (6110-30)
Reader composite video (with VITC, or as a reference for the LTC code
translator) is buffered on the separate I/O module by Q6 & Q5 and fed to
the VITC reader header J1. It is also AC coupled into the sync separator
by C29. The sync tips are clamped to -0.3 volts by germanium diode D5.
Comparator U11 detects the negative sync tips when compared to ground
reference and provides a logic level composite sync signal (SYNC) at pin 7.
Composite sync is integrated by U18f to derive vertical sync (VSYNC),
which interrupts the MCU. A field 2 pulse is generated by U9a and U10.
6.6.4. High Speed VITC Reader (6111-30)
The clock and data separator circuitry for the VITC reader is contained on a
separate sub-module which connects to the main circuit card via header
J1. Composite video, VSYNC, and some control signals from the MCU are
fed up the header from the main circuit board.
Composite video is buffered and DC restored by Q2, U14 and associated
components, to provide REF VIDEO to comparator U15, which recovers
VITC data from the DC restored video. U16 and associated components
provide a reference level to U15, of approximately one half the peak VITC
level, to ensure proper extraction of the VITC data regardless of the video
level.
Model 4025 Film Footage Encoder Manual
A constant
Page 6-20
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