Waveform Generator Signals And Registers - Intel 8XC196MC User Manual

9.2

WAVEFORM GENERATOR SIGNALS AND REGISTERS

Table 9-1 describes the waveform generator's signals, and Table 9-2 briefly describes the control
and status registers.
Waveform
Port
Generator
Pin
Signal
P6.0 WG1#
P6.1 WG1
P6.2 WG2#
P6.3 WG2
P6.4 WG3#
P6.5 WG3
— EXTINT
.
Table 9-2. Waveform Generator Control and Status Registers
Mnemonic Address
INT_MASK1 0013H
INT_PEND1 0014H
PI_MASK 1FBCH
(MC, MD)
PI_PEND 1FBEH
(MC, MD)
WG_COMP1 1FC2H
WG_COMP2 1FC4H
WG_COMP3 1FC6H
Table 9-1. Waveform Generator Signals
Type
O Waveform generator phase 1 negative output.
O Waveform generator phase 1 positive output.
O Waveform generator phase 2 negative output.
O Waveform generator phase 2 positive output.
O Waveform generator phase 3 negative output.
O Waveform generator phase 3 positive output.
I Input to the waveform generator's protection circuitry.
Interrupt Mask 1
The EXTINT bit enables or disables the EXTINT interrupt.
8XC196MH: The WG bit enables or disables the waveform generator
interrupt.
8XC196MC, MD: The PI bit enables or disables the multiplexed peripheral
interrupt. The corresponding bit in the PI_MASK register enables or disables
the individual sources of the peripheral interrupt.
Interrupt Pending 1
Any set bit indicates a pending interrupt request.
Peripheral Interrupt Mask
8XC196MC, MD: The WG bit enables or disables the waveform generator
interrupt as one of the possible sources of the multiplexed peripheral
interrupt. The PI bit in INT_MASK1 must be set to enable the multiplexed
peripheral interrupt.
Peripheral Interrupt Pending
Any set bit indicates a pending interrupt request.
Waveform Generator Compare Buffers
Each phase compare buffer contains a value that is compared with the
counter value. The action that is performed when a match occurs depends
on the operating mode.
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WAVEFORM GENERATOR
Description
Description
9-3