Intel 8XC196MC User Manual page 101

8XC196MC, MD, MH USER'S MANUAL
PTSSEL
The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt
service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit
selects a standard interrupt service routine. When PTSCOUNT reaches zero, hardware clears the
corresponding PTSSEL bit. The PTSSEL bit must be set manually to re-enable the PTS channel.
15
8XC196MC —
7
COMP2
15
8XC196MD —
7
COMP2
15
8XC196MH —
7
COMP3
Bit
Number
15 Reserved; for compatibility with future devices, write zero to this bit.
†
14:0 Setting a bit causes the corresponding interrupt to be handled by a PTS microcode routine.
The PTS interrupt vector locations are as follows:
Bit Mnemonic
EXTINT
PI (MC, MD)
WG (MH)
EPA5 (MD)
SPI (MH)
COMP4 (MD)
RI1 (MH)
EPA4 (MD)
RI0 (MH)
COMP3 (MC, MD) 2052H
TI1 (MH)
EPA3 (MC, MD)
††
PTS service is not useful for multiplexed interrupts because the PTS cannot readily
determine the source of these interrupts.
†
On the 8XC196MC device bits 10–12 are reserved. For compatibility with future devices, write zeros
to these bits.
5-14
EXTINT PI
EPA2 COMP1 EPA1
EXTINT PI EPA5
EPA2 COMP1 EPA1
EXTINT WG
COMP2 COMP1 EPA1
PTS Vector
205CH
††
205AH
205AH
2058H
††
2058H
2056H
2056H
2054H
2054H
2052H
2050H
Figure 5-6. PTS Select (PTSSEL) Register
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Reset State:
— — —
COMP0 EPA0
COMP4 EPA4
COMP0 EPA0
SPI RI1 RI0
COMP0 EPA0
Function
Bit Mnemonic
TI0 (MH)
COMP2 (MC,MD)
COMP3 (MH)
EPA2 (MC, MD)
COMP2 (MH)
COMP1
EPA1
COMP0
EPA0
AD
††
OVRTM
Address: 0004H
0000H
8
COMP3 EPA3
0
AD OVRTM
8
COMP3 EPA3
0
AD OVRTM
8
TI1 TI0
0
AD OVRTM
PTS Vector
2050H
204EH
204EH
204CH
204CH
204AH
2048H
2046H
2044H
2042H
2040H