Intel 8XC196MC User Manual page 108

INT_PEND
When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7
MC, MD COMP2
7
MH COMP3 COMP2
Bit
Number
7:0 Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is cleared
when processing transfers to the corresponding interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic
COMP2 (MC, MD) EPA Compare Channel 2
COMP3 (MH)
EPA2 (MC, MD)
COMP2 (MH)
COMP1
EPA1
COMP0
EPA0
AD
†
OVRTM
†
Timer 1 and timer 2 can generate the multiplexed overflow/underflow interrupt. Write to
PI_MASK to enable the interrupt sources; read PI_PEND to determine which source
caused the interrupt.
Figure 5-10. Interrupt Pending (INT_PEND) Register
EPA2 COMP1 EPA1
COMP1 EPA1
Interrupt
EPA Compare Channel 3
EPA Capture/Compare Channel 2
EPA Compare Channel 2
EPA Compare Channel 1
EPA Capture/Compare Channel 1
EPA Compare Channel 0
EPA Capture/Compare Channel 0
A/D Conversion Complete
Overflow/Underflow Timer
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STANDARD AND PTS INTERRUPTS
Reset State:
COMP0 EPA0
COMP0 EPA0
Function
Standard Vector
200EH
200EH
200CH
200EH
200AH
2008H
2006H
2004H
2002H
2000H
Address: 0009H
00H
0
AD OVRTM
0
AD OVRTM
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