Intel 8XC196MC User Manual page 503

8XC196MC, MD, MH USER'S MANUAL
INT_MASK1
INT_MASK1
The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests.
(The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can
be read from or written to as a byte register. PUSHA saves this register on the stack and POPA
restores it.
7
8XC196MC NMI
7
8XC196MD NMI
7
8XC196MH NMI
Bit
Number
†
7:0 Setting a bit enables the corresponding interrupt.
The standard interrupt vector locations are as follows:
Bit Mnemonic
NMI
EXTINT
PI (MC, MD)
WG (MH)
EPA5 (MD)
SPI (MH)
COMP4 (MD)
RI1 (MH)
EPA4 (MD)
RI0 (MH)
COMP3 (MC, MD) EPA Compare Channel 3
TI1 (MH)
EPA3 (MC, MD)
TI0 (MH)
††
The waveform generator and the EPA compare-only channel 5 can generate this
interrupt. Write to PI_MASK to enable the interrupt sources; read PI_PEND to
determine which source caused the interrupt.
†††
SIO 0 and SIO 1 can generate this interrupt. Write to PI_MASK to enable the interrupt
sources; read PI_PEND to determine which source caused the interrupt.
†
On the 8XC196MC device bits 4–3 are reserved. For compatibility with future devices, write zeros to
these bits.
C-26
EXTINT PI
EXTINT PI EPA5
EXTINT WG
Interrupt
Nonmaskable Interrupt
EXTINT pin
††
Multiplexed Peripheral Interrupt
Waveform Generator
EPA Capture/Compare Channel 5
†††
Serial Port
EPA Compare Channel 4
SIO 1 Receive
EPA Capture/Compare Channel 4
SIO 0 Receive
SIO 1 Transmit
EPA Capture/Compare Channel 3
SIO 0 Transmit
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— — —
COMP4 EPA4
SPI RI1 RI0
Function
Address: 0013H
Reset State: 00H
COMP3 EPA3
COMP3 EPA3
TI1 TI0
Standard Vector
203EH
203CH
203AH
203AH
2038H
2038H
2036H
2036H
2034H
2034H
2032H
2032H
2030H
2030H
0
0
0