Intel 8XC196MC User Manual page 571

8XC196MC, MD, MH USER'S MANUAL
JVT instruction, A-3, A-5, A-23, A-45, A-50, A-56
L
Latency‚ See bus-hold protocol‚ interrupts
LCALL instruction, A-3, A-23, A-45, A-50, A-56
LD instruction, A-2, A-23, A-44, A-49, A-55
LDB instruction, A-2, A-23, A-44, A-49, A-55
LDBSE instruction, A-3, A-24, A-44, A-49, A-55
LDBZE instruction, A-3, A-24, A-44, A-49, A-55
Level-sensitive input, B-13
Literature, 1-11
LJMP instruction, A-2, A-24, A-49, A-55
Logical instructions, A-48, A-53
LONG-INTEGER, defined, 3-4
Lookup tables, software protection, 3-11
M
Manual contents, summary, 1-1
Manuals, online, 1-10
Measurements, defined, 1-5
Memory bus, 2-6
Memory controller, 2-4, 2-6
Memory map, 4-1, 4-2
Memory mapping
auto programming mode, 16-27
Memory partitions, 4-1–4-19
chip configuration bytes, 4-4
chip configuration registers, 4-4
interrupt and PTS vectors, 4-3
OTPROM, 16-2
program memory, 4-2, 16-2
register file, 4-9
register RAM, 4-10
reserved memory, 4-3
security key, 4-4
SFRs, 4-4
special-purpose memory, 4-2, 4-3, 16-2
Memory protection, 16-3–16-7
CCR security-lock bits, 16-17
UPROM security bits, 16-7
Memory space, See memory partitions
Microcode engine, 2-4
Miller effect, 13-7
Mode 0, SIO, 7-5
Mode 1, SIO, 7-7
Mode 2, SIO, 7-9
Mode 3, SIO, 7-9
Index-6
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Mode 4, SIO, 7-6
Modified quick-pulse algorithm, 16-9
MUL instruction, A-25, A-46, A-48, A-53
MULB instruction, A-25, A-46, A-48, A-53
Multiprocessor communications
SIO port, 7-8, 7-9
MULU instruction, A-3, A-26, A-42, A-43, A-46,
A-48, A-53
MULUB instruction, A-3, A-26, A-42, A-43,
A-48, A-53
N
Naming conventions, 1-3–1-4
NEG instruction, A-2, A-27, A-41, A-48, A-53
Negative (N) flag, A-4, A-5, A-18, A-19, A-20
NEGB instruction, A-2, A-27, A-41, A-48, A-53
NMI, 5-3, 5-4, 5-6, B-16
hardware considerations, 5-6
idle, powerdown, reset status, B-24, B-25
Noise, reducing, 6-3, 6-4, 6-7, 12-12, 12-13, 13-4,
13-5, 13-6
NOP instruction, 3-11, A-3, A-27, A-46, A-51,
A-57
two-byte‚ See SKIP instruction
NORML instruction, 3-4, A-3, A-27, A-41, A-51,
A-57
NOT instruction, A-2, A-28, A-41, A-48, A-53
Notational conventions, 1-3–1-4
NOTB instruction, A-2, A-28, A-41, A-48, A-53
Numbers, conventions, 1-4
O
ONCE mode, 2-11, 14-10
entering, 14-11
exiting, 14-11
ONCE#, 14-2, B-17
Ones register, C-29
Opcodes, A-41
EE, and unimplemented opcode interrupt,
A-3, A-46
FE, and signed multiply and divide, A-3
map, A-2
reserved, A-3, A-46
Operand types, See data types
Operands, addressing, 3-10
Operating modes, 2-11
OR instruction, A-2, A-28, A-43, A-48, A-53