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8XC196MC, MD, MH USER'S MANUAL
Figure
8XC196M x Block Diagram ...........................................................................................2-3
2-1
2-2
Block Diagram of the Core ...........................................................................................2-3
2-3
Clock Circuitry ..............................................................................................................2-7
2-4
Internal Clock Phases ..................................................................................................2-8
4-1
Register File Memory Map ...........................................................................................4-9
4-2
Windowing ..................................................................................................................4-12
4-3
Window Selection (WSR) Register.............................................................................4-13
5-1
Flow Diagram for PTS and Standard Interrupts ...........................................................5-2
5-2
Waveform Generator Protection Circuitry.....................................................................5-7
5-3
Flow Diagram for the OVRTM Interrupt........................................................................5-8
5-4
Standard Interrupt Response Time ............................................................................5-11
5-5
PTS Interrupt Response Time ....................................................................................5-11
5-6
PTS Select (PTSSEL) Register ..................................................................................5-14
5-7
Interrupt Mask (INT_MASK) Register.........................................................................5-15
5-8
Interrupt Mask 1 (INT_MASK1) Register....................................................................5-16
5-9
Peripheral Interrupt Mask (PI_MASK) Register..........................................................5-17
5-10
Interrupt Pending (INT_PEND) Register ....................................................................5-21
5-11
Interrupt Pending 1 (INT_PEND1) Register ...............................................................5-22
5-12
Peripheral Interrupt Pending (PI_PEND) Register .....................................................5-23
5-13
PTS Control Blocks ....................................................................................................5-25
5-14
PTS Service (PTSSRV) Register ...............................................................................5-26
5-15
PTS Mode Selection Bits (PTSCON Bits 7:5) ............................................................5-27
5-16
PTS Control Block — Single Transfer Mode ..............................................................5-28
5-17
PTS Control Block — Block Transfer Mode ...............................................................5-31
5-18
PTS Control Block – A/D Scan Mode .........................................................................5-33
5-19
PTS Control Block 1 – Serial I/O Mode ......................................................................5-38
5-20
PTS Control Block 2 – Serial I/O Mode ......................................................................5-41
5-21
Synchronous SIO Transmit Mode Timing...................................................................5-43
5-22
Synchronous SIO Transmit Mode — End-of-PTS Interrupt Routine Flowchart..........5-46
5-23
Synchronous SIO Receive Timing..............................................................................5-47
5-24
Synchronous SIO Receive Mode — End-of-PTS Interrupt Routine Flowchart...........5-50
5-25
Asynchronous SIO Transmit Timing...........................................................................5-51
5-26
Asynchronous SIO Transmit Mode — End-of-PTS Interrupt Routine Flowchart........5-54
5-27
Asynchronous SIO Receive Timing............................................................................5-55
5-28
Asynchronous SIO Receive Mode — End-of-PTS Interrupt Routine Flowchart.........5-58
6-1
Standard Input-only Port Structure ...............................................................................6-3
6-2
Bidirectional Port Structure...........................................................................................6-8
6-3
Address/Data Bus (Ports 3 and 4) Structure ..............................................................6-15
6-4
Output-only Port .........................................................................................................6-18
6-5
Port 6 Output Configuration (WG_OUTPUT) Register ...............................................6-18
7-1
SIO Block Diagram .......................................................................................................7-1
7-2
Typical Shift Register Circuit for Mode 0 ......................................................................7-5
7-3
Mode 0 Timing..............................................................................................................7-6
7-4
Serial Port Frames for Mode 1 .....................................................................................7-8
xii
FIGURES
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