Intel 8XC196MC User Manual page 514

PI_PEND
When hardware detects a pending peripheral or timer interrupt, it sets the corresponding bit in the
interrupt pending (INT_PEND or INT_PEND1) registers and the peripheral interrupt pending
(PI_PEND) register. When the vector is taken, the hardware clears the INT_PEND/INT_PEND1
pending bit. Reading this register clears all the PI_PEND bits. Software can generate an interrupt by
setting a PI_PEND bit.
7
8XC196MC —
7
8XC196MD —
7
8XC196MH —
Bit Bit
Number Mnemonic
7, 5, 3, 1 —
6 — (MC)
COMP5 (MD)
SP1 (MH)
4 WG (MC, MD) Waveform Generator
SP0 (MH)
2 OVRTM2
— — WG
COMP5 — WG
SP1 — SP0
Reserved. These bits are undefined.
Reserved. This bit is undefined.
EPA Compare Channel 5
When set, this bit indicates a pending EPA compare channel 5 interrupt.
The EPA compare channel 5 and the waveform generator interrupts are
associated with the peripheral interrupt (PI). Setting INT_MASK1.5
enables PI. Setting PI_MASK.6 enables COMP5.
Serial Port 1 Error
When set, this bit indicates a pending serial port 1 error interrupt.
The serial port 1 and 0 error interrupts are associated with the serial port
interrupt (SPI). Setting INT_MASK1.4 enables SPI. Setting PI_MASK.6
enables SP1.
When set, this bit indicates a pending waveform generator interrupt.
The waveform generator and the EPA compare channel 5 interrupts are
associated with the peripheral interrupt (PI). Setting INT_MASK1.5
enables PI. Setting PI_MASK.5 enables WG.
Serial Port 0 Error
When set, this bit indicates a pending serial port 0 error interrupt.
The serial port 0 and 1 error interrupts are associated with the serial port
interrupt (SPI). Setting INT_MASK1.4 enables SPI. Setting PI_MASK.4
enables SP0.
Timer 2 Overflow/Underflow
When set, this bit indicates a pending timer 2 overflow/underflow interrupt.
The timer 2 and timer 1 overflow/underflow interrupts are associated with
the overflow/underflow timer interrupt (OVRTM). Setting INT_MASK.0
enables OVRTM. Setting PI_MASK.2 enables OVRTM2.
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Address:
Reset State:
— OVRTM2
— OVRTM2
— OVRTM2
Function
REGISTERS
PI_PEND
1FBEH
AAH
0
— OVRTM1
0
— OVRTM1
0
— OVRTM1
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