Intel 8XC196MC User Manual page 528

SP x _CON
x = 0–1 (8XC196MH)
The serial port control (SP x _CON) register selects the communications mode and enables or disables
the receiver, parity checking, and nine-bit data transmission.
7
8XC196MH M2
Bit Bit
Number Mnemonic
7 M2
6 DIR
5 PAR
4 TB8
3 REN
2 PEN
1:0 M1:0
DIR PAR TB8
See description for bits 0 and 1.
Synchronous Clock Direction
This bit determines the direction of the clock during synchronous mode.
0 = output
1 = input
Parity Selection Bit
This bit selects even or odd parity.
0 = even parity
1 = odd parity
Transmit Ninth Data Bit
This is the ninth data bit that will be transmitted in mode 2 or 3. This bit is
cleared after each transmission, so it must be set before SBUF x _TX is
written. When parity is enabled (SP x _CON.2 = 1), this bit takes on the
even parity value.
Receive Enable
Setting this bit enables receptions. When this bit is set, a falling edge on
the RXD x pin starts a reception in mode 1, 2, or 3. In mode 0, this bit must
be clear for transmission to begin and must be set for reception to begin.
Clearing this bit stops a reception in progress and inhibits further
receptions. To avoid a partial or undesired reception, clear this bit before
clearing the RI flag in SP x _STATUS. This can be handled in an interrupt
environment by using software flags or in straight-line code by using the
interrupt pending register to signal the completion of a reception.
Parity Enable
In modes 1 and 3, setting this bit enables the parity function. This bit must
be cleared if mode 2 is used. When this bit is set, TB8 takes the parity
value on transmissions and SP x _STATUS.7 becomes the receive parity
error bit.
Mode Selection
These bits along with bit 7 select the communications mode.
M2 M1 M0
0 0 0 synchronous mode 0
X 0 1 mode 1
X 1 0 mode 2
X 1 1 mode 3
1 0 0 synchronous mode 4
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Address:
Reset State:
REN PEN M1
Function
REGISTERS
SPx_CON
1F83H, 1F8BH
00H
0
M0
C-51