Intel 8XC196MC User Manual page 113

8XC196MC, MD, MH USER'S MANUAL
PTSSRV
The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has
been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corre-
sponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the
end-of-PTS interrupt is called, hardware clears the PTSSRV bit. The PTSSEL bit must be set manually
to re-enable the PTS channel.
15
8XC196MC —
7
COMP2
15
8XC196MD —
7
COMP2
15
8XC196MH —
7
COMP3
Bit
Number
15 Reserved. This bit is undefined.
†
14:0 A bit is set by hardware to request an end-of-PTS interrupt for the corresponding interrupt
through its standard interrupt vector.
The PTS interrupt vector locations are as follows:
Bit Mnemonic
EXTINT
PI (MC, MD)
WG (MH)
EPA5 (MD)
SPI (MH)
COMP4 (MD)
RI1 (MH)
EPA4 (MD)
RI0 (MH)
COMP3 (MC, MD) 2052H
TI1 (MH)
EPA3 (MC, MD)
††
PTS service is not useful for multiplexed interrupts because the PTS cannot readily
determine the source of these interrupts.
†
On the 8XC196MC device bits 10–12 are reserved. These bits are undefined.
5-26
EXTINT PI
EPA2 COMP1 EPA1
EXTINT PI EPA5
EPA2 COMP1 EPA1
EXTINT WG
COMP2 COMP1 EPA1
PTS Vector
205CH
††
205AH
205AH
2058H
††
2058H
2056H
2056H
2054H
2054H
2052H
2050H
Figure 5-14. PTS Service (PTSSRV) Register
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Reset State:
— — —
COMP0 EPA0
COMP4 EPA4
COMP0 EPA0
SPI RI1 RI0
COMP0 EPA0
Function
Bit Mnemonic
TI0 (MH)
COMP2 (MC,MD)
COMP3 (MH)
EPA2 (MC, MD)
COMP2 (MH)
COMP1
EPA1
COMP0
EPA0
AD
††
OVRTM
Address: 0006H
0000H
8
COMP3 EPA3
0
AD OVRTM
8
COMP3 EPA3
0
AD OVRTM
8
TI1 TI0
0
AD OVRTM
PTS Vector
2050H
204EH
204EH
204CH
204CH
204AH
2048H
2046H
2044H
2042H
2040H