Bus Width And Multiplexing - Intel 8XC196MC User Manual

8XC196MC, MD, MH USER'S MANUAL
CCR1 (Continued)
The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing
mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width.
7
1 1
Bit Bit
Number Mnemonic
1 IRC2
0 0
†
The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after reset, unless
the microcontroller is entering programming modes (see "Entering Programming Modes" on page
16-13), in which case the programming chip configuration bytes (PCCBs) are used. The CCBs
reside in nonvolatile memory at addresses 2018H (CCB0) and 201AH (CCB1).
Figure 15-2. Chip Configuration 1 (CCR1) Register

15.3 BUS WIDTH AND MULTIPLEXING

The external bus can operate as either a 16-bit multiplexed address/data bus or as a multiplexed
16-bit address/8-bit data bus (Figure 15-3).
15-10
0 1
Ready Control
This bit, along with IRC0 (CCR0.4), IRC1 (CCR0.5), and the READY pin
determine the number of wait states that can be inserted into the bus
cycle. While READY is held low, wait states are inserted into the bus
cycle until the programmed number of wait states is reached. If READY is
pulled high before the programmed number of wait states is reached, no
additional wait states will be inserted into the bus cycle.
IRC2 IRC1 IRC0
0 0 0 zero wait states
0 X 1 illegal
1 1 X illegal
1 0 0 one wait state
1 0 1 two wait states
1 1 0 three wait states
1 1 1 infinite
If you choose the infinite wait states option, you must keep P5.6
configured as the READY signal. Also, be sure to add external hardware
to count wait states and pull READY high within a specified time.
Otherwise, a defective external device could tie up the address/data bus
indefinitely.
Reserved; for compatibility with future devices, write zero to this bit.
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WDE BW1
Function
†
no direct access
0
IRC2 0