Intel 8XC196MC User Manual page 513

8XC196MC, MD, MH USER'S MANUAL
PI_MASK
PI_MASK (Continued)
The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests
associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow
timer interrupt (OVRTM).
7
8XC196MC
—
7
8XC196MD —
7
8XC196MH —
Bit Bit
Number Mnemonic
0 OVRTM1
C-36
— — WG
COMP5 — WG
SP1 — SP0
Timer 1 Overflow/Underflow
Setting this bit enables the timer 1 overflow/underflow interrupt.
The timer 1 and timer 2 overflow/underflow interrupts are associated with
the overflow/underflow timer interrupt (OVRTM). Setting INT_MASK.0
enables OVRTM.
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Address:
Reset State:
— OVRTM2
— OVRTM2
— OVRTM2
Function
1FBCH
AAH
0
— OVRTM1
0
— OVRTM1
0
— OVRTM1