Security Features; Controlling Access To Internal Memory - Intel 8XC196MC User Manual

Address Range
(Hex)
9FFF (MH)
2080
5FFF (MC, MD)
2080
207F
205E
205D
2040
203F
2030
202F
2020
201F
201C
201B
201A
2019
2018
2017
2014
2013
2000

16.3 SECURITY FEATURES

Several security features enable you to control access to both internal and external memory. Read
and write protection bits in the chip configuration register (CCR0), combined with a security key,
allow various levels of internal memory protection. Two UPROM bits disable fetches of instruc-
tions and data from external memory. (See Figure 16-1 on page 16-7 for more information.)

16.3.1 Controlling Access to Internal Memory

The lock bits in the chip configuration register (CCR0) control access to the OTPROM. The reset
sequence loads the CCRs from the CCBs for normal operation and from the PCCBs when enter-
ing programming modes. You can program the CCBs using any of the programming methods, but
only slave and PCCB programming modes allow you to program the PCCBs.
The developers have made a substantial effort to provide an adequate program
protection scheme. However, Intel cannot and does not guarantee that these
protection methods will always prevent unauthorized access.
Table 16-1. 87C196M x OTPROM Memory Map
Program memory
Program memory
Reserved (each location must contain FFH)
PTS vectors
Upper interrupt vectors
Security key
Reserved (each location must contain FFH)
Reserved (must contain 20H)
CCB1
Reserved (must contain 20H)
CCB0
Reserved (each location must contain FFH)
Lower interrupt vectors
NOTE
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PROGRAMMING THE NONVOLATILE MEMORY
Description
16-3