Intel 8XC196MC User Manual page 481

8XC196MC, MD, MH USER'S MANUAL
Table C-2. Register Name, Address, and Reset Status (Continued)
Register
Mnemonic
P7_PIN (MD)
P1_REG (MH)
P2_REG
P3_REG
P4_REG
P5_REG (MC, MD)
P5_REG (MH)
P7_REG (MD)
PI_MASK
PI_PEND
PPW
PSW
PTSSEL
PTSSRV
PWM_COUNT
PWM_PERIOD
PWM0_CONTROL
PWM1_CONTROL
SBUF0_RX (MH)
SBUF1_RX (MH)
SBUF0_TX (MH)
SBUF1_TX (MH)
SP
SP0_BAUD (MH)
SP1_BAUD (MH)
SP0_CON (MH)
SP1_CON (MH)
SP0_STATUS (MH)
SP1_STATUS (MH)
†
Reset value is FFH when pin is not driven.
††
Reset value is 80H if the EA# pin is high, A9H if EA# is low.
†††
The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after a device reset,
unless the device is entering programming modes (see "Entering Programming Modes" on page
16-13), in which case the programming chip configuration bytes (PCCBs) are used. The CCBs reside in
internal nonvolatile memory at addresses 2018H (CCB0) and 201AH (CCB1).
C-4
Register Name
Port 7 Pin Input
Port 1 Data Output
Port 2 Data Output
Port 3 Data Output
Port 4 Data Output
Port 5 Data Output
Port 7 Data Output
Peripheral Interrupt Mask
Peripheral Interrupt Pending
Programming Pulse Width
Processor Status Word
PTS Select
PTS Service
PWM Count
PWM Period
PWM 0 Control
PWM 1 Control
Serial Port Receive Buffer
Serial Port Receive Buffer
Serial Port Transmit Buffer
Serial Port Transmit Buffer
Stack Pointer
Serial Port 0 Baud Rate
Serial Port 1 Baud Rate
Serial Port Control
Serial Port Control
Serial Port Status
Serial Port Status
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Binary Reset Value
Hex
Addr
High
1FD7
1F9D
1FD4
1FFC
1FFD
1FF5
1FD5
1FBC
1FBE
no direct
access
0004 0000 0000
0006 0000 0000
1FB6
1FB4
1FB0
1FB2
1F80
1F88
1F82
1F8A
0018 XXXX XXXX
1F84 0000 0000
1F8C 0000 0000
1F83
1F8B
1F81
1F89
Low
XXXX XXXX
1111 1111
1111 1111
1111 1111
1111 1111
†
1111 1111
1111 1111
1010 1010
1010 1010
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
XXXX XXXX
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000