Intel 8XC196MC User Manual page 482

Table C-2. Register Name, Address, and Reset Status (Continued)
Register
Mnemonic
T1CONTROL
T2CONTROL
T1RELOAD
TIMER1
TIMER2
USFR (MC, MD)
USFR (MH)
WATCHDOG
WG_COMP1
WG_COMP2
WG_COMP3
WG_CONTROL (MC, MD)
WG_CONTROL (MH)
WG_COUNTER
WG_OUTPUT
WG_PROTECT (MC, MD)
WG_PROTECT (MH)
WG_RELOAD
WSR
ZERO_REG
†
Reset value is FFH when pin is not driven.
††
Reset value is 80H if the EA# pin is high, A9H if EA# is low.
†††
The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after a device reset,
unless the device is entering programming modes (see "Entering Programming Modes" on page
16-13), in which case the programming chip configuration bytes (PCCBs) are used. The CCBs reside in
internal nonvolatile memory at addresses 2018H (CCB0) and 201AH (CCB1).
Register Name
Timer 1 Control
Timer 2 Control
Timer 1 Reload
Timer 1 Value
Timer 2 Value
UPROM Special Function
Watchdog Timer
Waveform Gen Phase Comp 1
Waveform Gen Phase Comp 2
Waveform Gen Phase Comp 3
Waveform Gen Control
Waveform Gen Count
Waveform Gen Output Config
Waveform Gen Protection
Waveform Gen Reload
Window Selection
Zero Register
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Binary Reset Value
Hex
Addr
High
1F78
1F7C
1F72 XXXX XXXX
1F7A 0000 0000
1F7E 0000 0000
1FF6
000A
1FC2 0000 0000
1FC4 0000 0000
1FC6 0000 0000
0000 0000
1FCC
1000 0000
1FCA XXXX XXXX
1FC0 0000 0000
1FCE
1FC8 0000 0000
0014
0000 0000 0000
REGISTERS
Low
0000 0000
0000 0000
XXXX XXXX
0000 0000
0000 0000
0000 0010
XXXX XXXX
XXXX XXXX
0000 0000
0000 0000
0000 0000
1100 0000
0000 0000
XXXX XXXX
0000 0000
1111 0000
1110 0000
0000 0000
0000 0000
0000 0000
C-5