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INT_MASK
The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests.
(The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the
low byte of the processor status word (PSW). PUSHF or PUSHA saves the contents of this register
onto the stack and then clears this register. Interrupt calls cannot occur immediately following this
instruction. POPF or POPA restores it.
7
MC, MD
COMP2
7
MH
COMP3
COMP2
Bit
Number
7:0
Setting a bit enables the corresponding interrupt.
The standard interrupt vector locations are as follows:
Bit Mnemonic
COMP2 (MC, MD) EPA Compare-only Channel 2
COMP3 (MH)
EPA2 (MC, MD)
COMP2 (MH)
COMP1
EPA1
COMP0
EPA0
AD
†
OVRTM
†
Both timer 1 and timer 2 can generate the multiplexed overflow/underflow interrupt. Write
to PI_MASK to enable the interrupt sources; read PI_PEND to determine which source
caused the interrupt.
EPA2
COMP1
EPA1
COMP1
EPA1
Interrupt
EPA Compare-only Channel 3
EPA Capture/Compare Channel 2
EPA Compare Channel 2
EPA Compare Channel 1
EPA Capture/Compare Channel 1
EPA Compare Channel 0
EPA Capture/Compare Channel 0
A/D Conversion Complete
Overflow/Underflow Timer
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Reset State:
COMP0
EPA0
COMP0
EPA0
Function
Standard Vector
200EH
200EH
200CH
200EH
200AH
2008H
2006H
2004H
2002H
2000H
REGISTERS
INT_MASK
Address:
0008H
00H
0
AD
OVRTM
0
AD
OVRTM
C-25
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