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8XC196MC, MD, MH USER'S MANUAL
The receiver checks for a valid stop bit. Unless a stop bit is found within the appropriate time, the
framing error (FE) bit in the SPx_STATUS register is set. When the stop bit is detected, the data
in the receive shift register is loaded into SBUFx_RX and the receive interrupt (RI) flag is set. If
this happens before the previous byte in SBUFx_RX is read, the overrun error (OE) bit is set.
SBUFx_RX always contains the latest byte received; it is never a combination of the last two
bytes.
The receive interrupt (RI) flag indicates whether an incoming data byte has been received. The
transmit interrupt (TI) flag indicates whether a data byte has finished transmitting. These flags
also set the corresponding bits in the interrupt pending register. A reception or transmission sets
the RI or TI flag in SPx_STATUS and the corresponding interrupt pending bit. However, a soft-
ware write to the RI or TI flag in SPx_STATUS has no effect on the interrupt pending bits and
does not cause an interrupt. Similarly, reading SPx_STATUS clears the RI and TI flags, but does
not clear the corresponding interrupt pending bits. The RI and TI flags in the SPx_STATUS and
the corresponding interrupt pending bits can be set even if the RIx and TIx interrupts are masked.
The transmitter empty (TXE) bit is set if SBUFx_TX and its buffer are empty and ready to accept
up to two bytes. TXE is cleared as soon as a byte is written to SBUFx_TX. One byte may be writ-
ten if TI alone is set. By definition, if TXE has just been set, a transmission has completed and TI
is set.
The received parity error (RPE) flag or the received bit 8 (RB8) flag applies for parity enabled or
disabled, respectively. If parity is enabled, RPE is set if a parity error is detected. If parity is dis-
abled, RB8 is the ninth data bit received in modes 2 and 3.
7-16
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