Enabling The Serial Port Interrupts - Intel 8XC196MC User Manual

8XC196MC, MD, MH USER'S MANUAL
For mode 0 receptions, the BAUD_VALUE must be 0002H or greater.
Otherwise, the resulting data in the receive shift register will be incorrect.
The reason for this restriction is that the receive shift register is clocked from
an internal signal rather than the signal on TXDx. Although these two signals
are normally synchronized, the internal signal generates one clock before the
first pulse transmitted by TXDx and this first clock signal is not synchronized
with TXDx. This clock signal causes the receive shift register to shift in
whatever data is present on the RXDx pin. This data is treated as the least-
significant bit (LSB) of the reception. The reception then continues in the
normal synchronous manner, but the data received is shifted left by one bit
because of the false LSB. The seventh data bit transmitted is received as the
most-significant bit (MSB), and the transmitted MSB is never shifted into the
receive shift register.
Using XTAL1 at 16 MHz, the maximum baud rates are 2.76 Mbaud (SPx_BAUD = 8002H or
0002H) for mode 0 and 1.0 Mbaud for modes 1, 2, and 3. Table 7-3 shows the SPx_BAUD values
for common baud rates when using a 16 MHz XTAL1 clock input. Because of rounding, the
BAUD_VALUE formula is not exact and the resulting baud rate is slightly different than desired.
Table 7-3 shows the percentage of error when using the sample SPx_BAUD values. In most cases,
a serial link will work with up to a 5.0% difference in the receiving and transmitting baud rates.
Table 7-3. SP x _BAUD Values When Using XTAL1 at 16 MHz
Baud Rate
9600
4800
2400
1200
300
†
Bit 15 is always set when XTAL1 is selected as the clock source for the baud-rate generator.
7.4.4

Enabling the Serial Port Interrupts

Each serial port channel has both a transmit interrupt (TIx) and a receive interrupt (RIx). Each
channel can also generate a serial port receive error interrupt (SPx). To enable an interrupt, set the
corresponding mask bit in the interrupt mask register or peripheral interrupt mask register (see
Table 7-2 on page 7-2) and execute the EI instruction to globally enable servicing of interrupts.
See Chapter 5, "Standard and PTS Interrupts," for more information about interrupts.
7-14
CAUTION
SP x _BAUD Register Value
Mode 0 Mode 1, 2, 3
8340H 8067H
8682H 80CFH
8D04H 81A0H
9A0AH 8340H
E82BH 8D04H
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†
Mode 0, 4
0.04
0.02
0.01
0
0
% Error
Mode 1, 2, 3
0.16
0.16
0.08
0.04
0.01