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Logic Analyzer Concepts
Transitional Mode Theory (1660E/ES/EP-series only)
Transitional Mode Theory (1660E/ES/EP-series
only)
In Transitional acquisition mode, the timing analyzer samples data at
regular intervals, but only stores data when there is a transition
between logic levels on currently assigned bits of a pod pair. Each time
a level transition occurs on any of the bits, all bits of the pod pair are
stored. A time tag is stored with each stored data sample so the
measurement can be reconstructed and displayed later.
One issue when using transitional timing is how many transitions can
be stored. The number depends on the mode and frequency of
transition occurrence. The following overview explains the number of
transitions stored for each transitional timing mode and why.
125-MHz Transitional mode
When the timing analyzer runs in the 125-MHz mode, it operates like
the state analyzer with Count Time turned on, the exceptions being
that the store qualification comes from transition detectors instead of
the sequencer and that the analyzer uses an internal clock.
With 4 K of memory per channel and Count Time selected, the analyzer
uses half its memory (2 K) to store time tags. Because each pod pair
must store transitions at its own rate, each pod pair must store its own
set of time tags. This is why you do not have the option of using a free
pod to retain full memory as you have in the normal state mode.
When a transition is detected after a sample with no detected
transition, both samples are stored. If the next sample also indicates a
transition, only one sample is stored. If the next sample does not
indicate a transition, no sample is stored this time and the next
transition again stores two samples.
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Troubleshooting
