Hp 1660E/Es/Ep-Series Configuration Capabilities - Agilent Technologies HP 1660E Series User Manual

Logic Analyzer Reference

HP 1660E/ES/EP-Series Configuration Capabilities

HP 1660E/ES/EP-Series Configuration
Capabilities
The four analyzer models in each of the HP 1660E/ES/EP-series offer a
wide variety of channel widths and memory depth combinations. The
number of data channels range from 34 channels with the
HP 1663E/ES/EP, to a maximum of 136 channels with the
HP 1660E/ES/EP. In addition, a half-channel acquisition mode is
available which doubles memory depth from 4 K to 8 K per channel
while reducing channel width by half.
The configuration guide below illustrates the memory depth/channel
width combinations in all acquisition modes with all analyzer models.
State Analyzer Configurations
Mode HP 1660E/ES/EP
8K-deep / 68 chan.
Half-channel 65 data + 3 data or
100 MHz clock
4K-deep / 136 chan.
Full-channel 130 data + 6 data or
100 MHz clock
State Analyzer Configuration Considerations
• Unused clock channels can be used as data channels.
• With Time or State tags turned on, memory depth is reduced by half.
252
HP 1661E/ES/EP
8K-deep / 51 chan.
48 data + 3 data or
clock
4K-deep / 102 chan.
96 data + 6 data or
clock
However, full depth is retained if you leave one pod pair unassigned.
HP 1662E/ES/EP HP 1663E/ES/EP
8K-deep / 34 chan. 8K-deep / 17 chan.
32 data + 2 data or 16 data + 1 data or
clock clock
4K-deep / 68 chan. 4K-deep / 34 chan.
64 data +4 data or 32 data + 2 data or
clock clock