Timing Analyzer; State Analyzer - Agilent Technologies HP 1660E Series User Manual

Logic analyzers

Table of Contents

Logic Analyzer Concepts

The Trigger Sequence

Timing analyzer

When you configure a timing analyzer, the trigger sequence follows the

general outlines given previously. The trigger sequence of the timing

analyzer differs from the state analyzer in the following ways:

• There are 10 levels available to build a trigger.

• The trigger term is always the last step.

• The HP 1670E timing analyzer cannot use pattern terms h and j.

• The timing analyzer has two additional resources, Edge1 and Edge2.

• Edge1 and Edge2 recognize occurrences of a glitch, rising edge, falling

edge, either edge, or no edge on a bit or ORed set of bits.

When you configure a state analyzer, the trigger sequence follows the

general outlines given previously. The trigger sequence of the state

analyzer differs from the timing analyzer in the following ways:

• There are 12 levels available to build a trigger.

• The trigger term is never the last step.

• The state analyzer cannot use Edge1 and Edge2.

• The HP 1670E state analyzer can use pattern terms h and j.