Table of Contents
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Specifications
General Information
Logic levels
Data inputs
Clock outputs
Clock input
Internal clock period
External clock period (user supplied)
External duty cycle
Maximum number of "IF condition"
blocks at 50 MHz
Maximum number for different Macros
Maximum number of lines in a Macro
Maximum number of Macro invocations
Maximum number of repeat loop invocations 1000
Maximum number of Wait event patterns
462
TTL, 3-state, TTL/3.3v,
3-state TTL/CMOS, ECL terminated,
ECL Unterminated, and differential
ECL (without POD)
3-bit pattern - level sensing (clock pod)
Synchronized to output data
DC to 200 MHz
Programmable from 5 ns to 250 us
in a 1, 2, 2.5, 4, 5, 8 sequence
DC to 200 MHz
2 ns minimum high time
1
100
1024
1000
4
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Troubleshooting
