Hp 1660E/Es/Ep-Series Logic Analyzer Description - Agilent Technologies HP 1660E Series User Manual

Logic Analyzer Reference

HP 1660E/ES/EP-Series Logic Analyzer Description

HP 1660E/ES/EP-Series Logic Analyzer
Description
The HP 1660E/ES/EP-series logic analyzers are part of a family of
general-purpose logic analyzers. The HP 1660E-series consists of four
models ranging in channel width from 34 channels to 136 channels,
with 100-MHz state and 500-MHz timing speeds. The HP 1660ES-series
is the HP 1660E-series with a built in 2-GSa/s digitizing oscilloscope,
and similarly the HP 1660EP-series has a built in 200 M Vector/s
pattern generator.
The HP 1660E/ES/EP-series logic analyzers are all designed as full-
featured standalone or network-configurable instruments for use by
digital and microprocessor hardware and software designers. All
models have HP-IB, RS-232-C, and Centronics interfaces for hard copy
printouts and control by a host computer, and have ethernet LAN
interfaces.
Analyzer memory depth is 4 K per channel in all pod pair groupings, or
8K per channel on one pod of a pod pair (half-channel mode).
Oscilloscope memory is 32K samples. Pattern generator memory is
258,048 vectors.
Measurement data is displayed as data listings and waveforms, and can
also be plotted on a chart or compared to a reference image. Profiled
data is displayed as histograms of activity by time, state, or address
range.
The 100-MHz state analyzer has master, master/slave, and
demultiplexed clocking modes available. Measurement data can be
stamped with state or time tags. For triggering and data storage, the
state analyzer uses 12 sequence levels with two-way branching, 10
pattern resource terms, 2 range terms, and 2 timers.
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