Master And Slave Clock Fields (State Only) - Agilent Technologies HP 1660E Series User Manual

Logic analyzers
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Logic Analyzer Reference
The Analyzer Format Menu

Master and Slave Clock fields (State only)

The Master and Slave Clock fields are used to construct a clocking
arrangement. A clocking arrangement is the assignment of appropriate
clocks, clock edges, and clock qualifier levels which allow the analyzer
to synchronize itself on valid data.
Clock selections
When the Master or Slave Clock field is selected, a clock/qualifier
selection menu appears showing the available clocks and qualifiers for
a clocking arrangement. Depending on the model, there are a
maximum of six clocks available (J through P), and a maximum of four
clock qualifiers available (Q1 through Q4).
Clock/Qualifier Selection Menu
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This manual is also suitable for:

Hp 1660es seriesHp 1660ep series1670e series

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