Agilent Technologies HP 1660E Series User Manual page 317

Logic Analyzer Reference
The Analyzer Format Menu
Clock edges are ORed to clock edges, clock qualifiers are ANDed to
clock edges, and clock qualifiers can be either ANDed or ORed
together. All clock and qualifier combinations on the left side of the
graphic line are ORed to all combinations on the right side of the line.
For example, in a six-clock model, all combinations of the J, K, and L
clock with Q1 and Q2 qualifiers, are ORed to the clock combinations of
the M, N, and P clocks with Q3 and Q4 qualifiers.
"Pod Clock Field" found earlier in this chapter for information on
See Also
selecting clocking arrangement types, such as Master, Slave, or
Demultiplex.
Clock Fields
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