Agilent Technologies HP 1660E Series User Manual page 256

Logic Analyzer Reference
HP 1670E-Series Logic Analyzer Description
Analyzer Memory Depth and Channel Configurations
Mode
1
state 100 MHz
2
state 100 MHz
State compare 100 MHz
State compare 100 MHz
timing, half-channel
250 MHz
timing, full-channel
125 MHz
1
With tags turned off or non-interleaved tags. Tags are non-interleaved if there is an unassigned pod
pair or pod pair assigned to an analyzer that is turned off.
2
With interleaved tags.
State Analyzer Configuration Consideration
• Unused clock channels can be used as data channels.
• With Time or State tags turned on, maximum available memory depth is
256
Memory
1,040,384
516,096
253,952
1
122,880
2
2,088,960
1,040,384
reduced. However, full depth is retained if you leave on pod pair
unassigned.
Channel
Configuration
HP 1670E
136 chan. 132 data + 4
data or clock
136 chan. 132 data + 4
data or clock
68 chan. 66 data + 2
data or clock
136 chan. 132 data + 4
data or clock
HP 1671E HP 1672E
102 chan. 98 68 chan. 64
data + 4 data data + 4 data
or clock or clock
102 chan. 98 68 chan. 64
data + 4 data data + 4 data
or clock or clock
51 chan. 49 34 chan. 32
data + 2 data data + 2 data
or clock or clock
102 chan. 98 68 chan. 64
data + 4 data data + 4 data
or clock or clock