Gtx Transceivers - Xilinx KC705 User Manual

GTX Transceivers

[Figure
The KC705 board provides access to 16 GTX transceivers:
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The GTX transceivers in 7 Series FPGAs are grouped into four channels described as
Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below
the GTX Quad of interest. There are four GTX Quads on the KC705 board with connectivity
as shown here:
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Table 1-10
Table 1-10:
Transceiver Bank
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
1-2, callout 12]
Eight of the GTX transceivers are wired to the PCI Express® x8 endpoint edge
connector (P1) fingers
Four of the GTX transceivers are wired to the FMC HPC connector (J22)
One GTX is wired to the FMC LPC connector (J2)
One GTX is wired to SMA connectors (RX: J17, J18 TX: J19, J20)
One GTX is wired to the SFP/SFP+ Module connector (P5)
One GTX is used for the SGMII connection to the Ethernet PHY (U37)
Quad 115:
• No directly wired GTX input reference clocks
• Contains 4 GTX transceivers for PCI Express lanes 4-7
Quad 116:
• MGTREFCLK0 - Si5324 jitter attenuator
• MGTREFCLK1 - PCIe edge connector clock
• Contains 4 GTX transceivers for PCIe lanes 0-3
Quad 117:
• MGTREFCLK0 - SGMII clock
• MGTREFCLK1 - SMA clock
• Contains 4 GTX transceivers with one allocated for: SMA, SGMII, SFP, and FMC
LPC (DP0)
Quad 118:
• MGTREFCLK0 - FMC HPC GBT clock 0
• MGTREFCLK1 - FMC LPC GBT clock 0
• Contains 4 GTX transceivers for FMC HPC (DP0 - DP3)
lists the GTX interface connections to the FPGA (U1).
GTX Interface Connections for FPGA U1
Associated Net Name
MGT_BANK_115 GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y3
MGTREFCLK0
MGTREFCLK1
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Feature Descriptions
Connections
PCIe7
PCIe6
PCIe5
PCIe4
N/C
PCIe_CLK
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