Multi-Gigabit Transceivers (Gtx Mgts) - Xilinx ML605 User Manual

8. Multi-Gigabit Transceivers (GTX MGTs)

The ML605 provides access to 20 MGTs.
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X-Ref Target - Figure 1-10
Note: xxxMHz = user specified frequency
100 MHz in from
PCIe Fingers
(HCSL)
FMC#1 HPC xxx MHz LVDS GBTCLK0
AC coupling on Mezz
FMC#1 HPC CLK2_M2C
ICS
(LVDS)
854104
FMC#1 HPC xxx MHz LVDS GBTCLK1
AC coupling on Mezz
FMC#1 HPC CLK3_M2C
ICS
(LVDS)
854104
References
See the Virtex-6 FPGA GTX Transceivers User Guide.
ML605 Hardware User Guide
UG534 (v1.2.1) January 21, 2010
Eight (8) of the MGTs are wired to the PCIe x8 Endpoint (P1) edge connector fingers
Eight (8) of the MGTs are wired to the FMC HPC connector (J64)
One (1) MGT is wired to SMA connectors (J26, J27)
One (1) MGTs is wired to the FMC LPC connector (J63)
One (1) MGT is wired to the SFP Module connector (P4)
One (1) MGT is used for an SGMII connection to the Ethernet PHY (U80)
FMC#2 LPC xxxMHz GBTCLK0 LVDS
100 MHz LVDS
ICS874001
ICS
854104
No Connect
No Connect
(LVDS)
To FPGA CLK2_M2C_IO CC pin
(LVDS)
To FPGA CLK3_M2C_IO CC pin
Figure 1-10: MGT Clocking
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SGMII 125 MHz LVDS
SMA xxx MHz LVDS
AC coupling on Mezz
250 MHz LVDS
No Connect
[Ref 12]
Detailed Description
SGMII
GTX_X0Y19
SMA
GTX_X0Y18
REFCLK0
REFCLK1
SFP
GTX_X0Y17
GTX_X0Y16 FMC#2
GTX_X0Y15 PCIe Lane1
PCIe Lane 2
GTX_X0Y14
REFCLK0
REFCLK1
PCIe Lane 3
GTX_X0Y13
PCIe
PCIe Lane 4
GTX_X0Y12
PCIe Lane 5
GTX_X0Y11
PCIe Lane 6
GTX_X0Y10
REFCLK0
REFCLK1
GTX_X0Y09
PCIe Lane 7
GTX_X0Y08
PCIe Lane 8
GTX_X0Y07
FMC#1
GTX_X0Y06
FMC#1
REFCLK0
REFCLK1
GTX_X0Y05
FMC#1
PCIe
GTX_X0Y04
FMC#1
GTX_X0Y03 FMC#1
GTX_X0Y02
FMC#1
REFCLK0
REFCLK1
GTX_X0Y01
FMC#1
FMC#1
GTX_X0Y00
UG534_10_101409
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