User Push Buttons (Active High); Gtx Transceivers And Reference Clocks - Xilinx Kintex-7 FPGA KC724 User Manual

Figure 1-12
X-Ref Target - Figure 1-12

User Push Buttons (Active High)

Callout 26,
SW4 and SW5 are active-High user push buttons that are connected to user I/O pins on the
FPGA as shown in
Table 1-11: User Push Buttons

GTX Transceivers and Reference Clocks

Callout 27,
The KC724 board provides access to all GTX transceiver and reference clock pins on the
FPGA as shown in
RX-TX lanes. Four lanes are referred to as a Quad.
Note:
KC724 GTX Transceiver Characterization Board
UG932 (v2.2) October 10, 2014
Shows the user test I/O connector J125.
Figure 1-2.
Table 1-11. These switches can be used for any purpose.
FPGA (U1)
Pin Function
K18 User push button
G19 User push button
Figure 1-2.
Figure 1-13. The GTX transceivers are grouped into four sets of four
Figure 1-13 is for reference only and might not reflect the current revision of the board.
www.xilinx.com
J125
1 2 USER_SW1
3 4
USER_SW2
5 6 USER_SW3
7 8 USER_SW4
9 10
USER_SW5
11 12 USER_SW6
GND
UG932_C1_12_062712
Figure 1-12: User Test I/O
Direction IOSTANDARD
Input LVCMOS18
Input LVCMOS18
Detailed Description
Schematict Net Reference
Name Designator
USER_PB1 SW5
USER_PB2 SW4
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