Gtx Transceivers - Xilinx ZC706 User Manual

X-Ref Target - Figure 1-16
X4
114.285 MHz
20 ppm
2
GND1
GND2
4
GND
REC_CLOCK_C_P
REC_CLOCK_C_N
SI5324_INT_ALM
SI5324_RST
See the Silicon Labs Si5324 data sheet

GTX Transceivers

[Figure 1-2, callout 12]
The ZC706 board provides access to 16 GTX transceivers:
• Four of the GTX transceivers are wired to the PCI Express x4 endpoint edge connector
(P4) fingers
• Eight of the GTX transceivers are wired to the FMC HPC connector (J37)
• One GTX transceiver is wired to the FMC LPC connector (J5)
• One GTX transceiver is wired to SMA connectors (RX: J32, J33 TX: J35, J34)
• One GTX transceiver is wired to the SFP/SFP+ Module connector (P2)
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
SI5324_VCC
1
XA SI5324_XTAL_XA
3
XB SI5324_XTAL_XB
C138
0.1 μF 25V
X5R
REC_CLOCK_P
R251 0.1W
100Ω 1%
REC_CLOCK_N
NC
C141
0.1 μF 25V
NC
X5R
NC
NC 11
NC 15
NC 18
R89
4.7 KΩ 5%
GND
Figure 1-16: Jitter Attenuated Clock
www.xilinx.com
U60
Si5324C-C-GM
Clock Multiplier/
Jitter Attenuator
2
5
NC
VDD1 NC1
9
10 NC
VDD2 NC2
14
32 NC
VDD3 NC3
30
6
NC
XA NC4
33
NC
NC5
29
7 SI5324_OUT_N
XB CKOUT1_N
28
SI5324_OUT_P
CKOUT1_P
16
35
NC
CKIN1_P
CKOUT2_P
34
NC
CKOUT2_N
17
CKIN1_N
12
CKIN2_P
13
CKIN2_N
37
GNDPAD
3 36
INT_C1B CMODE
4 27
C2B SDI
23
RATE0 SDA_SDO
22
RATE1 SCL
24
LOL A0
19 31
GND3 A1
20 31
GND4 A2_SS
9
1
RST_B
GND1
31
21
CS_CA
GND2
GND
[Ref 21].
Feature Descriptions
C137
0.1 μF 25V
X5R
SI5324_OUT_C_N
SI5324_OUT_C_P
C136
0.1 μF 25V
X5R
NC
RTC SI5324_SDA
RTC SI5324_SCL
UG954_c1_16_041113
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