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11.15 Interrupt Conditions
11.15.1 Interrupts that are generated for FCAN controller
When interrupts are enabled (condition <1>: M_CTRLn register's IE bit = 1, conditions other than <1>: C1IE
register's interrupt enable flag = 1), interrupts will be generated under the following conditions (n = 00 to 31).
<1> Message-related operation has succeeded
• When a message has been received in the receive message buffer
• When a remote frame has been received in the transmit message buffer
(when auto acknowledge mode has not been set, i.e., when the M_CTRLn register's RMDE0 bit = 0)
• When a message has been transmitted from the transmit message buffer
<2> When a CAN bus error has been detected
• Bit error
• Bit stuff error
• Form error
• CRC error
• ACK error
<3> When the CAN bus mode has been changed
• Error passive status elapsed while FCAN was transmitting
• Bus off status was set while FCAN was transmitting
• Error passive status elapsed while FCAN was receiving
<4> Internal error
• Overrun error
11.15.2 Interrupts that are generated for global CAN interface
Interrupts are generated for the global CAN interface under the following conditions.
• An undefined area is accessed
• If the GOM bit is cleared to 0 when one of the CAN modules is not in the initialization status (ISTAT bit of
C1CTRL register = 0) with the EFSD bit of the CGST register = 0
• A CAN module register (register starting with "C1") is accessed when the GOM bit of the CGST register = 0
• A temporary buffer (in the area following the address of the C1SYNC register) is accessed when the GOM bit of
the CGST register = 1
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CHAPTER 11 FCAN CONTROLLER
User's Manual U14492EJ3V0UD
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