Interrupt Servicing - NEC mPD78F0730 Preliminary User's Manual

12.7.2 Interrupt servicing

The following flowchart illustrates how an interrupt is serviced.
Remark
The following bits of the UF0ISn register are automatically cleared by hardware when a given condition is satisfied
(n = 1 to 3).
• E0INDT, E0ODT, SUCES, STG, and CPUDEC bits of UF0IS1 register
• BKI1DT bit of UF0IS2 register
• BKO1FL and BKO1DT bits of UF0IS3 register
Because clearing an interrupt source by the UF0ICn register is given a lower priority than setting an interrupt source
by hardware, the interrupt source may not be cleared depending on the timing (n = 0 to 4).
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CHAPTER 12 USB FUNCTION CONTROLLER (USBF)
Figure 12-13. Interrupt Servicing
START
INTUSBaB active
(a = 0 to 2)
INTUSB2B = 0?
Yes
Reading UF0IS4 register
SETINTC of UF0IC4
register = 0
Servicing interrupt
END
♦: Processing by hardware
Preliminary User's Manual U19014EJ1V0UD
No
Masking ID bit
INTUSB0B = 0?
Yes
(n = 0, 1)
Reading UF0ISn register
Target bit of UF0ICn
register = 0
No
(m = 2, 3)
Reading UF0ISm register
Target bit of UF0ICm
register = 0
359