YASKAWA FSDrive-MV1000 Parameter Manual page 83

No.
Name
(Addr.)
U6-07 q-Axis ACR
(5FH) Output
U6-08 d-Axis ACR
(60H) Output
U6-18 Speed Detection
(7CDH) PG1 Counter
U6-19 Speed Detection
(7E5H) PG2 Counter
Frequency
U6-20
Reference Bias
(7D4H)
(Up/Down 2)
U6-21
Offset Frequency
(7D5H)
U6-80 to
U6-99
Option Monitor
(7B0 to
1 to 20
7B9, 7F0
to 7F9H)
U9-01 Power Cell
(3400H) Status 1
U9-02 Power Cell
(3410H) Status 2
U9-03 Power Cell
(3420H) Status 3
U9-04 Power Cell
(3430H) Status 4
U9-05 Power Cell DC
(3440H) Bus Voltage 1
U9-06 Power Cell DC
(3450H) Bus Voltage 2
U9-07 Power Cell
(3460H) Temperature
U9-08 Power Cell
(3470H) Output Current
Power Cell
U9-09
Software No.
(3480H)
(CPU)
Power Cell
U9-10
Software No.
(3490H)
(FPGA)
<60> V/f Control: 10 V: drive rated power (kW), OLV and CLV: 10 V: motor capacity (E2-11)
YASKAWA ELECTRIC TOEP C710687 03B FSDrive-MV1000 Parameter Guide
V/f OLV
Displays the output value for current control relative to motor secondary
current (q-axis).
V/f OLV
Displays the output value for current control relative to motor secondary
current (d-axis).
All Modes
Monitors the number of pulses for speed detection (PG1).
All Modes
Monitors the number of pulses for speed detection (PG2).
All Modes
Displays the bias value used to adjust the frequency reference.
All Modes
Displays the frequency added to the main frequency reference.
All Modes
Displays a monitor value of option cards.
U9: Power Cell Monitors
All Modes
Displays the status 1 of each of the Power Cells in hexadecimal.
Bit 0 to F: ASIC status
All Modes
Displays the status 2 of each of the Power Cells in hexadecimal.
Bit 0 to F: Fault information 1
All Modes
Displays the status 3 of each of the Power Cells in hexadecimal.
Bit 0 to F: Fault information 2
All Modes
Displays the status 4 of each of the Power Cells in hexadecimal.
Higher two digits (8 bits): Switching
Lower two digits (8 bits): Number of communication errors
All Modes
Displays the DC bus voltage 1 (Vpc) of each Power Cell.
All Modes
Displays the DC bus voltage 2 (Vcn) of each Power Cell.
All Modes
Displays the temperature of each Power Cell.
All Modes
Displays the output current of each Power Cell.
All Modes
Displays the CPU ID of each Power Cell.
All Modes
Displays the FPGA ID of each Power Cell.
Description
CLV
CLV
common_TMonly
1.3 Parameter Table
Analog Output
Level
10 V: Drive
common
rated voltage
10 V: Drive
common
rated voltage
common_
10 V: 65536
common_
10 V: 65536
10 V: Max
common_
frequency
common_
–
No signal output
common_
available
common_
No signal output
available
common_
No signal output
available
No signal output
available
common_
No signal output
available
common_
10 V: 2000 V
common_
10 V: 2000 V
common_
10 V: 200°C
10 V: Drive
common_
rated current
No signal output
common_
available
No signal output
common_
available
Unit Page
0.1% –
0.1% –
1 pulse
1 pulse
0.1% –
0.1% –
– –
– –
– –
– –
– –
1 V –
1 V –
0.01°C –
0.1 A –
– –
– –
83