13. Watchdog Timer - Renesas R8C Series User Manual

R8C/1A Group, R8C/1B Group

13. Watchdog Timer

The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable. Table 13.1 lists information on the Count Source
Protection Mode.
Refer to 6.5 Watchdog Timer Reset for details on the watchdog timer reset.
Figure 13.1 shows the Block Diagram of Watchdog Timer and Figures 13.2 to 13.3 show Registers OFS, WDC,
WDTR, WDTS, and CSPR.
Table 13.1 Count Source Protection Mode
Item
Count source
Count operation
Reset condition of watchdog
timer
Count start condition
Count stop condition
Operation at time of underflow
CPU clock
Write to WDTR register
Internal
reset signal
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
Figure 13.1 Block Diagram of Watchdog Timer
Rev.1.30 Dec 08, 2006
REJ09B0252-0130
Count Source Protection Mode
CPU clock
Decrement
• Reset
• Write 00h to the WDTR register before writing FFh
• underflow
Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Stop mode, wait mode
Watchdog timer interrupt or
watchdog timer reset
Prescaler
WDC7 = 0
1/16
1/128
WDC7 = 1
fRING-S
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Disabled
Low-speed on-chip oscillator
clock
None
Watchdog timer reset
CSPRO = 0
Watchdog timer
CSPRO = 1
13. Watchdog Timer
Count Source Protection Mode
Enabled
PM12 = 0
Watchdog timer
interrupt request
PM12 = 1
Watchdog
timer reset
Set to
(1)
7FFFh
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register