Gth Quad Reset In Response To Gthreset - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features
12. Change RXRATE<n>[1:0] to the value used for the application and wait for
13. Change RXPOWERDOWN<n>[1:0] to 2'b00.
14. Wait for RXCTRLACK<n> to go High.
15. Pulse RXBUFRESET for one RXUSERCLKIN clock cycle. The receiver is ready for
X-Ref Target - Figure 2-7
GSR
GTHINITDONE
TXRATE <n>[1:0]
SAMPLERATE<n>[2:0]
TXPOWERDOWN<n>[1:0]
TXBUFRESET<n>
TXCTRLACK<n>
RXRATE<n>[1:0]
RXPOWERDOWN<n>[1:0]
RXCTRLACK<n>
RXBUFRESET<n>
Figure 2-7: GTH Transceiver Initialization when in Divided Line Rate Mode
Note relevant to
1.

GTH Quad Reset in Response to GTHRESET

GTHRESET is used as a reset to all four GTH lanes within the Quad, including the PLL.
Besides resetting the GTH Quad, GTHRESET also changes the Quad to its default
configuration of 10GBASE-R. If the GTH Quad has a different configuration from the
default of 10GBASE-R, the design must also assert GTHINIT after GTHRESET is
deasserted.
Figure 2-8
GTHRESET when the GTH transceiver is configured in full line rate mode (i.e., the
TXRATE<n>[1:0], SAMPLERATE<n>[2:0], and RXRATE<n>[1:0] ports are set to all zeros).
Follow these steps to reset the GTH transceiver, when configured in full line rate mode:
1.
2.
3.
4.
5.
62
RXCTRLACK to go High.
normal operation.
2'b00
3'b000
2'b10
2'b00
Figure 2-7:
The TXCTRLACK<n> and RXCTRLACK<n> signals can be High for more than
1 DCLK clock cycle.
shows the reset sequence of the GTH Quad following the assertion of
Set PCS_MODE_LANE<n>[7:4] and PCS_MODE_LANE<n>[3:0] to the datapath
mode used in the application for RX and TX, respectively.
Set PCS_RESET_LANE<n> to the datapath mode used in the application.
Set PCS_RESET_1_LANE<n> to the datapath mode used in the application.
Set TXPOWERDOWN<n>[1:0] and RXPOWERDOWN<n>[1:0] to 2'b10.
Assert GTHRESET for 1 DCLK clock cycle. The TXCTRLACK<n> and
RXCTRLACK<n> ports from all four lanes are asserted.
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USER_TXRATE
USER_SAMPLERATE
2'b10
Virtex-6 FPGA GTH Transceivers User Guide
2'b00
USER_RXRATE
2'b00
UG371_c2_04_082609
UG371 (v2.0) February 16, 2010