Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter
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Ports and Attributes

Table 3-14
Table 3-14: TX Configurable Driver Ports
98
Power down
Floating: TXP and TXN should float High to VTTX (assuming AC-coupled mode)
Near-end PCS loopback and Near-end PMA loopback
TXP and TXN are transmitting live data
defines the TX configurable driver ports.
Port Dir
TXDEEMPH0 In
TXDEEMPH1
TXDEEMPH2
TXDEEMPH3
TXMARGIN0[2:0] In
TXMARGIN1[2:0]
TXMARGIN2[2:0]
TXMARGIN3[2:0]
TXN0 Out
(Pad)
TXN1
TXN2
TXN3
TXP0
TXP1
TXP2
TXP3
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Clock Domain
TXUSERCLKIN0 Reserved. Tie this input to 0.
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
TXUSERCLKIN0 Reserved. Tie these inputs to 000.
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
TX Serial Clock TXP and TXN are the differential
output pairs for each of the
transmitters in the GTHE1_QUAD
primitive. These ports represent pads.
The location of these ports must be
constrained and brought to the top
level of the design.
Virtex-6 FPGA GTH Transceivers User Guide
Description
UG371 (v2.0) February 16, 2010