Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter

Ports and Attributes

Table 3-3
Table 3-3: FPGA TX Interface Ports
Port
GTHX4LANE
TXBUFRESET0
TXBUFRESET1
TXBUFRESET2
TXBUFRESET3
TXCTRL0[7:0]
TXCTRL1[7:0]
TXCTRL2[7:0]
TXCTRL3[7:0]
TXDATA0[63:0]
TXDATA1[63:0]
TXDATA2[63:0]
TXDATA3[63:0]
TXDATAMSB0[7:0]
TXDATAMSB1[7:0]
TXDATAMSB2[7:0]
TXDATAMSB3[7:0]
TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
TXUSERCLKOUT0
TXUSERCLKOUT1
TXUSERCLKOUT2
TXUSERCLKOUT3
78
defines the FPGA TX interface ports.
Dir Clock Domain
In Async
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In N/A
Out N/A
www.xilinx.com
Description
When this port is asserted, GTH lanes 0, 1, 2, and 3 are
configured into a single x4 link.
This port resets the buffer inside the TX data converter. Both the
internal TX clock and TXUSERCLKIN<n> must be stable before
a reset can be applied to the buffer.
These inputs either indicate control of TXDATA<n> or they are
used as an extension of TXDATA<n> depending on the mode
selected in the transmitter datapath:
8B/10B: These inputs are asserted when TXDATA<n> is an
8B/10B K character.
TXCTRL<n>[7] corresponds to TXDATA<n>[63:56]
TXCTRL<n>[6] corresponds to TXDATA<n>[55:48]
TXCTRL<n>[5] corresponds to TXDATA<n>[47:40]
TXCTRL<n>[4] corresponds to TXDATA<n>[39:32]
TXCTRL<n>[3] corresponds to TXDATA<n>[31:24]
TXCTRL<n>[2] corresponds to TXDATA<n>[23:16]
TXCTRL<n>[1] corresponds to TXDATA<n>[15:8]
TXCTRL<n>[0] corresponds to TXDATA<n>[7:0]
64B/66B: These inputs are 64B/66B control bits.
Raw mode: These inputs are used as part of TXDATA<n>[71:64].
This input bus is the transmit data bus of the transmit interface
from the FPGA.
This bus extends the transmit data bus as TXDATA<n>[79:72].
This port provides a clock for the internal transmitter PCS
datapath. It is a buffered version of the TXUSERCLKOUT<n>.
This clock must be stable for the RXCTRLACK<n> and
RXRATE<n> ports to be active.
This port is the transmit parallel clock output based on the
transmitter data bus width, TXRATE<n>, and
SAMPLERATE<n>. This clock is used to drive
TXUSERCLKIN<n> through a buffer.
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010