Guide Contents; Additional Documentation - Xilinx Virtex-6 FPGA User Manual

About This Guide
This document describes how to use the GTH transceivers in Virtex®-6 FPGAs. In this
document:
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Guide Contents

This manual contains the following chapters:
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Additional Documentation

The following documents are also available for download at
http://www.xilinx.com/support/documentation/virtex-6.htm.
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Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Virtex-6 FPGA GTH transceiver is abbreviated as GTH transceiver.
GTHE1_QUAD is the name of the instantiation primitive that instantiates one
Virtex-6 FPGA GTH transceiver.
A Quad is a cluster or set of four GTH transceivers that share two differential reference
clock pin pairs and analog supply pins.
GTH lane [n] refers to a specific lane within the GTH Quad, where n = 0, 1, 2, or 3.
The terms FPGA logic and fabric refer to internal FPGA circuitry not including the
GTH transceiver.
Chapter 1, Transceiver and Tool Overview
Chapter 2, Shared Transceiver Features
Chapter 3, Transmitter
Chapter 4, Receiver
Chapter 5, Board Design Guidelines
Virtex-6 Family Overview
The features and product selection of the Virtex-6 family are outlined in this overview.
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-6 family.
Virtex-6 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
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Preface
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