Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver

Ports and Attributes

Table 4-21
.
Table 4-21: FPGA RX Interface Ports
Port Dir
GTHX4LANE In
RXBUFRESET0 In
RXBUFRESET1
RXBUFRESET2
RXBUFRESET3
RXCODEERR0[7:0] Out
RXCODEERR1[7:0]
RXCODEERR2[7:0]
RXCODEERR3[7:0]
RXCTRL0[7:0] Out
RXCTRL1[7:0]
RXCTRL2[7:0]
RXCTRL3[7:0]
132
defines the FPGA RX interface ports.
Clock Domain
Async When this port is asserted, GTH lanes 0, 1, 2, and 3 are configured
into a single x4 link.
RXUSERCLKIN0 This port resets the buffer inside the RX data converter. Both the
internal RX clock and RXUSERCLKIN<n> must be stable before a
RXUSERCLKIN1
reset can be applied to the buffer.
RXUSERCLKIN2
RXUSERCLKIN3
RXUSERCLKIN0 These outputs indicate an error occurred on RXDATA<n> or they are
used as an extension of RXDATA<n> depending on the mode
RXUSERCLKIN1
selected in the receive datapath:
RXUSERCLKIN2
8B/10B: These outputs indicate that RXDATA<n> is the result of an
RXUSERCLKIN3
8B/10B code error.
RXCODEERR<n>[7] corresponds to RXDATA<n>[63:56]
RXCODEERR<n>[6] corresponds to RXDATA<n>[55:48]
RXCODEERR<n>[5] corresponds to RXDATA<n>[47:40]
RXCODEERR<n>[4] corresponds to RXDATA<n>[39:32]
RXCODEERR<n>[3] corresponds to RXDATA<n>[31:24]
RXCODEERR<n>[2] corresponds to RXDATA<n>[23:16]
RXCODEERR<n>[1] corresponds to RXDATA<n>[15:8]
RXCODEERR<n>[0] corresponds to RXDATA<n>[7:0]
64B/66B: RXCODEERR<n>[0] indicates a 64B/66B code error.
RXCODEERR<n>[7:1] are not used for this mode.
Raw mode: These outputs are used as part of RXDATA<n>[79:72].
RXUSERCLKIN0 These outputs indicate the status of RXDATA<n> or they are used as
an extension of RXDATA<n> depending on the mode selected in the
RXUSERCLKIN1
receive datapath:
RXUSERCLKIN2
8B/10B: These outputs are asserted when RXDATA<n> is an 8B/10B
RXUSERCLKIN3
K character.
RXCTRL<n>[7] corresponds to RXDATA<n>[63:56]
RXCTRL<n>[6] corresponds to RXDATA<n>[55:48]
RXCTRL<n>[5] corresponds to RXDATA<n>[47:40]
RXCTRL<n>[4] corresponds to RXDATA<n>[39:32]
RXCTRL<n>[3] corresponds to RXDATA<n>[31:24]
RXCTRL<n>[2] corresponds to RXDATA<n>[23:16]
RXCTRL<n>[1] corresponds to RXDATA<n>[15:8]
RXCTRL<n>[0] corresponds to RXDATA<n>[7:0]
64B/66B: These outputs are 64B/66B control bits.
Raw mode: These outputs are used as part of RXDATA<n>[71:64].
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Description
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010