Xilinx Virtex-6 FPGA User Manual page 73

Figure 2-16
interface.
X-Ref Target - Figure 2-16
DISABLEDRP
MGMTPCSLANESEL[3:0]
MGMTPCSMMDADDR[4:0]
MGMTPCSREGADDR[15:0]
MGMTPCSREGWR
MGMTPCSWRDATA[15:0]
MGMTPCSREGRD
MGMTPCSRDACK
MGMTPCSRDDATA[15:0]
Figure 2-16: Management Interface Write Access Timing Diagram
The write access consists of the MMD, GTH lane select, and register address signals, the
write data, and a single cycle pulse of the MGMTPCSREGWR signal. There is no
acknowledgment indicator for a write operation. The management interface supports
multiple write accesses by asserting the MGMTPCSREGWR signal as shown in Event 1 of
Figure
Multiple MGMTPCSLANESEL[3:0] signals can be asserted simultaneously for a write
access.
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
is a timing diagram for writing to the register through the management
DCLK
(Select MMD Address)
(Select Management Register Address)
2-16.
www.xilinx.com
(Select GTH Lane)
D1
Management Interface
(Event 1)
D2 D3
UG371_c2_13_020810
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