Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features
•
•
•
•

Ports and Attributes

Table 2-10
Table 2-10: Reset Ports
Port
DCLK
GTHINIT
GTHINITDONE
GTHRESET
RXBUFRESET0
RXBUFRESET1
RXBUFRESET2
RXBUFRESET3
56
Asserting GTHRESET not only resets the GTH Quad but also changes its
configuration back to its default of 10GBASE-R. For example, if the design is
configured for OC-192, asserting GTHRESET changes the configuration to
10GBASE-R.
To keep the user configuration after GTHRESET is deasserted, GTHINIT must be
pulsed.
Both TXUSERCLKIN<n> and RXUSERCLKIN<n> clocks must be stable when
TXPOWERDOWN<n> and RXPOWERDOWN<n> are set in normal operation mode.
The PCS_MODE_LANE<n>, PCS_RESET_LANE<n>, and PCS_RESET_1_LANE<n>
attributes must be set to the datapath mode configuration used in the application.
defines the reset ports.
Dir Clock Domain
In N/A
In DCLK
Out DCLK
In DCLK
In RXUSERCLKIN0
RXUSERCLKIN1
RXUSERCLKIN2
RXUSERCLKIN3
www.xilinx.com
Description
This input is the DRP interface clock. It is also used as the
management interface clock when the management
interface is enabled. This clock must be connected and
available all the time for the GTHE1_QUAD primitive to
initialize properly, even if the DRP or the management
interface is not used in the design.
This input triggers the programming of the attributes
setting from configuration memory to the registers in the
GTHE1_QUAD primitive.
This port must be asserted for 1 DCLK clock cycle.
This port is driven High upon completion of programming
the bits from the configuration memory to the registers in
the GTHE1_QUAD primitive.
This output is driven Low when GTHRESET or GTHINIT is
asserted. It remains Low until after the assertion of
GTHINIT.
This port resets the GTHE1_QUAD primitive. When this
port is asserted, the configuration of all GTH transceivers
within the GTHE1_QUAD primitive reverts to the default
setting of 10GBASE-R. To maintain the same user
configuration, GTHINIT must be pulsed after GTHRESET
is deasserted.
This port must be asserted for 1 DCLK clock cycle.
This input resets the buffer inside the RX data converter (see
Figure 4-5, page 136). Both the internal RX clock and
(1)
RXUSERCLKIN<n> must be stable before a reset can be
applied to the buffer.
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010