Using Rx Pattern Checker - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver
Table 4-11
Table 4-11: RX Pattern Checker Registers (Read Only)
(1)
Register Name
PRBS_ERR_CNT0
PRBS_ERR_CNT1
PRBS_TIMER_0
PRBS_TIMER_1
PRBS_TIMER_2
Notes:
1. The DRP or the Management Interface must be used to access these registers.

Using RX Pattern Checker

For the read-only registers, the DRP or management interface can be used for monitoring
the PRBS error counter and the timer for PRBS testing.
•
116
defines the RX pattern checker registers.
Type
16-bit Hex PRBS error counter [31:16]. Counter for PRBS or 8B/10B errors.
16-bit Hex PRBS error counter [15:0]. Counter for PRBS or 8B/10B errors.
16-bit Hex PRBS timer [47:32]. Timer for PRBS mode testing or monitoring.
16-bit Hex PRBS timer [31:16]. Timer for PRBS mode testing or monitoring.
16-bit Hex PRBS timer [15:0]. Timer for PRBS mode testing or monitoring.
DRP Address
• PRBS_ERR_CNT0_LANE0: 0x5002
• PRBS_ERR_CNT0_LANE1: 0x5102
• PRBS_ERR_CNT0_LANE2: 0x5202
• PRBS_ERR_CNT0_LANE3: 0x5302
• PRBS_ERR_CNT1_LANE0: 0x5003
• PRBS_ERR_CNT1_LANE1: 0x5103
• PRBS_ERR_CNT1_LANE2: 0x5203
• PRBS_ERR_CNT1_LANE3: 0x5303
• PRBS_TIMER_0_LANE0: 0x5004
• PRBS_TIMER_0_LANE1: 0x5104
• PRBS_TIMER_0_LANE2: 0x5204
• PRBS_TIMER_0_LANE3: 0x5304
• PRBS_TIMER_1_LANE0: 0x5005
• PRBS_TIMER_1_LANE1: 0x5105
• PRBS_TIMER_1_LANE2: 0x5205
• PRBS_TIMER_1_LANE3: 0x5305
• PRBS_TIMER_2_LANE0: 0x5006
• PRBS_TIMER_2_LANE1: 0x5106
• PRBS_TIMER_2_LANE2: 0x5206
• PRBS_TIMER_2_LANE3: 0x5306
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Description
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010