Management Interface; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Management Interface

Functional Description

The management interface allows the dynamic change of parameters of the
GTHE1_QUAD primitive. It also allows monitoring the status of certain blocks within the
GTH transceiver.
The management interface has separate signals for the MMD, GTH lane, and register
address fields. This interface is driven by DCLK. When the management interface is
selected, the DRP interface must be disabled by setting the DISABLEDRP port.

Ports and Attributes

Table 2-16
.
Table 2-16: Management Interface Ports
Port
DCLK
DISABLEDRP
MGMTPCSLANESEL[3:0]
MGMTPCSMMDADDR[4:0]
MGMTPCSRDACK
MGMTPCSRDDATA[15:0]
MGMTPCSREGADDR[15:0]
MGMTPCSREGRD
MGMTPCSREGWR
MGMTPCSWRDATA[15:0]
There are no management interface attributes.
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
defines the management interface ports.
Dir Clock Domain
In N/A This input is the DRP interface clock. It is also used as the
management interface clock when the management interface is
enabled. This clock must be connected and available all the time
for the GTHE1_QUAD primitive to initialize properly, even if the
DRP or the management interface is not used in the design.
In DCLK This input switches between the DRP and the management
interface blocks.
0: DRP interface is selected.
1: Management interface is selected.
In DCLK These inputs select the GTH lane of the management interface:
0001: Select GTH lane 0.
0010: Select GTH lane 1.
0100: Select GTH lane 2.
1000: Select GTH lane 3.
The user can select more than one GTH lane for accessing the
registers.
In DCLK This input bus is the MMD address bus.
Out DCLK This output is the management interface read data valid signal.
It indicates when data is valid for read operations.
Out DCLK This output bus is the management interface register read data
bus.
In DCLK This input bus is the management interface register address bus.
In DCLK This input is the management interface read request valid signal.
In DCLK This input is the management interface write request valid
signal.
In DCLK This input bus is the management interface register write data
bus.
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Management Interface
Description
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