Using Power Down; Loopback; Functional Description; Far-End Loopback - Xilinx Virtex-6 FPGA User Manual

Table 2-13
.
Table 2-13: Power-Down Attributes

Using Power Down

To activate the power-down mode on a per lane basis, use either the POWERDOWN<n>
port or the GTH_CFG_PWRUP_LANE<n> attribute.
The TXPOWERDOWN and RXPOWERDOWN ports are used to activate the power down
on the transmitter or the receiver, respectively.

Loopback

Functional Description

The GTH transceiver supports these loopback modes:
•
•
•

Far-end Loopback

The Far-end loopback mode uses external equipment to generate and check test data. The
loopback occurs after passing the deserializer of the PMA. The entire PCS section is
bypassed except for the data multiplexers closest to the PMA. The loopback path works
only when the external test equipment uses the same reference clock as the PMA.
Figure 2-12
X-Ref Target - Figure 2-12
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
defines the power-down attributes.
Attribute
GTH_CFG_PWRUP_LANE0
GTH_CFG_PWRUP_LANE1
GTH_CFG_PWRUP_LANE2
GTH_CFG_PWRUP_LANE3
Far-end Loopback (line loopback)
Near-end PCS Loopback
Near-end PMA Loopback
shows the Far-end loopback datapath.
TXN/TXP
RX
RXN/RXP
Buffer
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Type
1-bit Binary This control attribute powers off the
corresponding lane. This attribute is set to
1'b1 to power up the corresponding GTH
lane.
PMA
Serializer
TX
Buffer
Deserializer
CDR
DFE
Figure 2-12: Far-end Loopback
Loopback
Description
PCS
UG371_c2_09_020510
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