Ports And Attributes; Using The Reference Clock - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features

Ports and Attributes

Table 2-1
primitive.
Table 2-1: Reference Clock Input Structure Ports for the GTHE1_QUAD Primitive
Table 2-2
primitive.
Table 2-2: Reference Clock Input Structure Ports for the IBUFDS_GTHE1 Primitive
Table 2-3
software primitive.
Table 2-3: Reference Clock Input Structure Attribute

Using the Reference Clock

The reference clock is always used in an AC-coupled mode. The recommended value for
the AC-coupling capacitors is 100 nF. The LVPECL clock must be used to drive the
reference clock pins. Refer to DS152, Virtex-6 FPGA Data Sheet: DC and Switching
Characteristics for electrical and switching specifications.
44
defines the reference clock input structure ports for the GTHE1_QUAD
Port Dir
REFCLK In
defines the reference clock input structure ports for the IBUFDS_GTHE1 software
Port Dir Clock Domain
I In
IB In
O Out
defines the reference clock input structure attribute for the GTHE1_QUAD
Attribute Type
PLL_CFG1 16-bit Binary
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Clock Domain
N/A REFCLK is an external clock driven by the
O port of the IBUFDS_GTHE1 software
primitive as the reference clock to the
GTHE1_QUAD primitive.
Async This port is the positive input of the reference
clock differential pair.
Async This port is the negative input of the reference
clock differential pair.
Async This port is the output of the reference clock
buffer connected to the REFCLK port of the
GTHE1_QUAD primitive.
This attribute defaults to 16'h8440.
[15]: REFCLK termination control (pll_refclk_term_b)
AC-coupled mode: 1'b1
Reserved: 1'b0
[14:0]: Reserved
Reserved: 15'h0440
Virtex-6 FPGA GTH Transceivers User Guide
Description
Description
Description
UG371 (v2.0) February 16, 2010