Revision History - Xilinx Virtex-6 FPGA User Manual

Revision History

The following table shows the revision history for this document.
Date Version
09/16/09 1.0
02/16/10 2.0
UG371 (v2.0) February 16, 2010
Initial Xilinx release.
Changed the clock domain for the RXPOWERDOWNx[1:0] ports in
page 56, and Table 2-12, page
Chapter 1: Updated OTU-3 values in
relocated ports I, IB, and O to new
Chapter 2: In the GTHRESET description in
be pulsed only after GTHRESET is deasserted. In
RXPOWERDOWN and TXPOWERDOWN descriptions for the x4 link case. Added
Clock Input Structure, page 43. Removed reference to LVDS clocks as being able to drive the
reference clock pins, page 44. Added sentence about MMCM and BUFR to TSTREFCLKOUT port
description in Table 2-4. Added
Table 2-11, changed the meaning of bit code 110 for bits [13:11] and [10:8] of the
PCS_MODE_LANE attribute to Reserved; changed the 8B/10B reset value for the
PCS_RESET_LANE attribute; added reference to the Virtex-6 FPGA GTH Transceiver Wizard to
attribute PCS_RESET_1_LANE, bits [15:2]. In
PMA_LPBK_CTRL_LANE attribute description; changed the Reserved bits for [13:11] and [10:8] in
the PCS_MODE_LANE attribute; added reference to the Virtex-6 FPGA GTH Transceiver Wizard
to attribute PMA_LPBK_CTRL_LANE, bits [15:2]. In
DO[15:0] to DRPDO[15:0]. Added note about DISABLEDRP to
and Using the Management Interface, page
Chapter 3: Added 32 and 64 bits to 8B/10B mode in
for 32-bit and 64-bit fabric interface data width in
settings for the BUFFER_CONFIG_LANE attribute in
code 110 for bits [13:11] and [10:8] of the PCS_MODE_LANE attribute to Reserved in
Table 3-6, Table 3-8, and Table
to attribute PCS_RESET_1_LANE, bits [15:2] in
PCS_RESET_LANE attribute in
the Virtex-6 FPGA GTH Transceiver Wizard to attribute PCS_RESET_1_LANE, bits [15:2] in
Table 3-10. Changed the PCS_RESET_LANE value in
Table 3-12, and added reference to the Virtex-6 FPGA GTH Transceiver Wizard to attribute
PRBS_CFG_LANE, bits [15:4] and PCS_RESET_1_LANE, bits [15:2]; changed the Reserved bits for
[13:11] and [10:8] in the PCS_MODE_LANE attribute. In
FPGA GTH Transceiver Wizard to attribute PCS_MISC_CFG_0_LANE, bits [15:12] and [5:0].
Added TX Configurable Driver.
Chapter 4: Added RX Analog Front
Virtex-6 FPGA GTH Transceiver Wizard to attribute PCS_MISC_CFG_0_LANE, bits [15:12] and
[5:0] in Table 4-8, and to attributes PCS_MISC_CFG_0_LANE, bits [15:12] and [5:0],
PCS_RESET_1_LANE bits [15:2], and PRBS_CFG_LANE bits [15:4] in
Description section of RX Pattern
PRBS31 mode, and added two sentences at the end of the section. Added
8B/10B reset value for the PCS_RESET_LANE attribute in
Table 4-18. Deleted PRBS checker reference in Description of RXCODEERR in
Table 4-15, Table 4-17, and Table
transmitter to receiver in the description of RX_FABRIC_WIDTH, and changed the meaning of bit
code 110 for bits [13:11] and [10:8] of the PCS_MODE_LANE attribute to Reserved. In
Table 4-16, and Table 4-18, added reference to the Virtex-6 FPGA GTH Transceiver Wizard to
attribute PCS_RESET_1_LANE, bits [15:2]. Changed the PCS_RESET_LANE value in
Enabling 8B/10B Mode, page
rows to 8B/10B Mode for 32-bit and 64-bit fabric interface data width in
manual adjustment mode settings for the BUFFER_CONFIG_LANE attribute in
Added Chapter 5, Board Design
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Revision
66.
Table 1-1. In Table 1-3, renamed DO port to DRPDO and
Table 1-4.
Table 2-7 and Table
Table 2-10
PLL, page 48. Revised Figure
Table 2-14, added the encoding to the
Table
72.
Table 3-1. Added two rows to 8B/10B Mode
Table 3-2. Revised manual adjustment mode
Table
3-10. Added reference to the Virtex-6 FPGA GTH Transceiver Wizard
Table 3-6. Changed the 8B/10B reset value for the
Table 3-6, Table 3-8, Table 3-10, and
step 2
Table
End, RX Equalization, and
Checker, added paragraph about when the checker is forced into
Table
4-21. In Table 4-13, Table 4-16,
130. Added 32 and 64 bits to 8B/10B mode in
Guidelines.
Virtex-6 FPGA GTH Transceivers User Guide
Table 1-3, page 15, Table 2-10,
2-10, indicated that GTHINIT must
and Table 2-12, changed
Reference
2-12, Figure 2-13, and Figure
2-15, changed the name of port
Using the DRP Interface, page 70
3-4, and changed the meaning of bit
Table
Table 3-12. Added reference to
of Enabling 8B/10B Mode, page
3-13, added reference to the Virtex-6
RX CDR. Added reference to the
Table 4-10. In the Functional
Table 4-9. Changed the
4-10, Table 4-13, Table 4-16, and
Table 4-12,
Table 4-18, and Table 4-22, changed
Table
step 2
Table 4-19. Added two
Table 4-20. Revised
Table 4-22.
2-14. In
3-4,
85. In
4-13,
of