Using The Management Interface - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features

Using the Management Interface

Follow these steps to enable the management interface:
1.
2.
One example for implementing the above sequence in logic is to tie the DISABLEDRP port
to the inverter of GTHINITDONE.
Note:
and the management interface, the user must wait two DCLK cycles for the change to take effect
before accessing the registers.
Figure 2-15
X-Ref Target - Figure 2-15
MGMTPCSREGADDR[15:0]
The read access consists of MMD, GTH lane select, register address signals, and a single
cycle pulse of the MGMTPCSREGRD signal. The read addresses must be held until the
read access completes and returns an acknowledgment through the MGMTPCSRDACK
signal. A read operation can be requested right after the acknowledgment indicator signal
as shown in Event 1 of
acknowledgment indicator signal.
72
Drive the DISABLEDRP port Low during GTH transceiver initialization.
When the GTHINITDONE signal goes High from completion of GTH transceiver
initialization, drive the DISABLEDRP port High.
When the setting on the DISABLEDRP port is changed to switch between the DRP interface
is a timing diagram for reading the register through the management interface.
DISABLEDRP
DCLK
MGMTPCSLANESEL[3:0]
MGMTPCSMMDADDR[4:0]
MGMTPCSREGWR
MGMTPCSWRDATA[15:0]
MGMTPCSREGRD
MGMTPCSRDACK
MGMTPCSRDDATA[15:0]
Figure 2-15: Management Interface Read Access Timing Diagram
Figure
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(Select GTH Lane)
(Select MMD Address)
(Select Management Register Address)
16'h0000
2-15. No read or write operation can be requested prior to the
Virtex-6 FPGA GTH Transceivers User Guide
(Event 1)
16'h0000
UG371_c2_12_020810
UG371 (v2.0) February 16, 2010